PLC2 – In-House-Training

Easy Start

• File I/O
  • File I/O with VHDL

How To

• Connectivity
  • Transceiver Overview
  • PCI Express Technology Overview
  • Memory Interface Overview
  • MIG: Memory Interface Generator
  • Ethernet MAC Overview

Methodik

• Schaltungstechnik
  • Entwurf digitaler kombinatorischer Systeme
  • Entwurf digitaler sequentieller Systeme
  • Arithmetische Grundschaltungen
  • Sequentielle Schaltwerke
    (State Machines FSM)
  • Zahlendarstellung
  • Grundschaltungen
    (Codewandler, Detektoren, Encoder, Decoder)
  • Meta Stabilität und Synchronisierschaltungen
     
• VHDL
  • Introduction to VHDL
  • Modeling with VHDL
  • VHDL Operators
  • Structural Modeling
  • Concurrent and Sequential Statements
  • Processes
  • The VHDL Testbench Concept
  • VHDL Type Concept
  • Generics
  • Finite State Machines
  • Subprograms
  • Loop Statements
  • Attributes: More Information about Objects
  • Define your own Packages
  • VHDL Build-In Packages
  • The Build-In Timing Model
  • Modeling external Components
  • Overview Assertion Based Verification
  • File I/O with VHDL
  • Generating the Simulus
  • Checking the Behaviour
  • Designing re-useable Components
  • Configuration and IP-Cores
     
• Verilog
  • Hardware Modeling Overview
  • Verilog Language Concepts
  • Modules and Ports
  • Introduction to Testbenches
  • Verilog Operators and Expressions
  • Data-Flow Level Modeling
  • Verilog Precedural Statements
  • Controlled Operation Statements
  • Verilog Tasks and Functions
  • Advanced Language Concepts
  • Finite State Machines
     
• PlanAhead
  • PlanAhead Software Benefits and
    Features Overview
  • I/O Pin Planning
  • CORE Generator Software Integration
  • Static Timing Analysis with the
    PlanAhead Software
  • Design Development and Analysis
  • Placing Dedicated Resources
  • Introduction to Pblocks
  • Floorplanning Techniques
  • Floorplanning Case Studies
  • Design Preservation with Partitions
  • Debugging with the ChipScope Pro Tool
  • Tcl Scripting in the PlanAhead Software
  • Team Design
  • Routing Optimization in Virtex-6 Devices
     
• ChipScope
   
• Partial Reconfiguration

Technologie

• Silicon
  • CoolRunner CPLDs
  • FPGA Overview
  • CLB Architecture
  • Slice Flip-Flops
  • Memory Resources
  • DSP Resources
  • I/O Resources
  • Clocking Resources
  • Memory Controllers
  • Dedicated Hardware
  • HDL Coding Techniques
     
• Software Options for Optimizations
   
• Timing Constraints
  • Timing Budget of digital circuits
  • Basic Constraints
  • Advanced Constraints
     
• Signal Integrity
  • General Introduction to SI Problems
  • Transmission Lines
  • SI-Models and Tools
  • Reflection
  • Crosstalk
  • SI System Analysis – General
  • SI System Analysis – Memory Interfaces
  • SI System Analysis – Serial Transceivers
  • Power Integrity – Basics
  • Power Integrity – Advanced
     
• FPGA Board Design
  • FPGA Requirements and Limitations for Board Design
  • Clocking Concepts and Realizations
  • Signal Interfacing Options and Realizations (SelectIO domain)
  • High-Speed Signal Interfacing Options and Realizations (transceiver domain)
  • Configuration Board Design
  • FPGA Power Supply –
    Requirements and Solutions
  • PCB Details for Board Planning /
    Design Process
  • FPGA Thermal Design

Applikationen

• Embedded Design
  • AXI IP Interface Overview
  • PicoBlaze Controller
  • MicroBlaze Controller
  • ZYNQ Controller
  • XPS Hardware Design Flow
  • SDK Software Design Flow
  • Creating Hardware Peripherals in XPS
  • Creating Software Drivers for
    User Peripherals
  • Linux for MicroBlaze: PetaLinux
  • Embedded Open Source Linux
     
• DSP
  • Matlab and Simulink for XILINX System Generator
  • XILINX System Generator Design Flow
  • Hardware Co-Simulation using
    XILINX System Generator
     
• General Connectivity
  • Connectivity Kits - Connectivity Targeted Reference Design Overview
  • Introduction to SelectIO Connectivity
  • Introduction to High-Speed Connectivity (Transceiver, Memory, PCIe)
     
• PCI Express
  • Introduction to the PCIe Architecture
  • Review of the PCIe Protocol
  • PCIe and the CORE Generator Interface
  • Simulating a PCIe System Design
  • Connecting Logic to the Core - AXI Interface
  • Packet Formatting Details
  • Endpoint Application Considerations
  • Application Focus: DMA
  • Virtex-6 FPGA Root Port
  • Compliance and Debugging
  • Interrupts and Error Management
  • Mechanicals, Hot Plus and Power
  • Connecting Logic to the Core - Local Link
     
• Serial Transceiver
      (general or transceiver / family specific)
  • Transceiver Overview
  • Basic Transceiver Principles (PCS Domain)
  • Transceiver Design
  • Transceiver Simulation
  • Transceiver Implementation
  • Transceiver Board Design
    (PCB, Power, Signal Interfacing)
  • Transceiver Signal Integrity
    (Basics, Simulation, Link Estimation)
  • Transceiver Test & Debugging
  • Physical Link Optimization
    (PMA layer options and tools)
  • Practical Example Designs / Labs on Real Hardware
  • Transceiver Applications (Protocols, Standards, Examples)
     
• High-Speed Memory Interfacing
  • Memory Devices
  • Memory Controller (all Families)
  • FPGA Resources for Memory Interfaces
  • Memory Interface Design
  • Memory Interface Simulation
  • Memory Interface Implementation
  • Memory Interface Board Design
    (PCB, Power, Signal Interfacing)
  • Memory Interface Signal Integrity Analysis